MAX5952CUAX+【PDF 31/50 页】IC PSE CNTRLR FOR POE 36-SSOP

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Sheet目录43

27页 28页 29页 30页 [31页]32页 33页 34页 35页

High-Power, Quad, PSE Controller

for Power-Over-Ethernet

______________________________________________________________________________________ 31

PGOOD_ is set to 1 (Table 14) at the end of the power-

up startup period if the power-good condition is met (0

< (V

OUT

- V

) < PG

). The power-good condition

must remain valid for more than t

PGOOD

to assert

PGOOD_. PGOOD_ is reset to 0 whenever the output

falls out of the power-good condition. A fault condition

immediately forces PGOOD_ low.

PWR_EN_ is set to 1 when the port power is turned on.

PWR_EN resets to 0 as soon as the port turns off. Any

transition of PGOOD_ and PWR_EN_ bits set the corre-

sponding bit in the power event registers R02h/R03h

(Table 8). A reset sets R10h = 00h.

Table 14. Power Status Register

ADDRESS = 10h

SYMBOL

BIT

R/W

DESCRIPTION

PGOOD4

Power-good condition on port 4

PGOOD3

Power-good condition on port 3

PGOOD2

Power-good condition on port 2

PGOOD1

Power-good condition on port 1

PWR_EN4

Power is enabled on port 4

PWR_EN3

Power is enabled on port 3

PWR_EN2

Power is enabled on port 2

PWR_EN1

Power is enabled on port 1

Table 15. Address Input Status Register

ADDRESS = 11h

SYMBOL

BIT

R/W

DESCRIPTION

Reserved

Device address, A3 pin latched-in status

Device address, A2 pin latched-in status

Device address, A1 pin latched-in status

Device address, A0 pin latched-in status

MIDSPAN

MIDSPAN inputs latched-in status

AUTO

AUTO inputs latched-in status

A3, A2, A1, A0 (Table 15) represent the four LSBs of

the MAX5952 address (Table 4). During a reset, the

device latches into R11h. These four bits address from

the corresponding inputs as well as the state of the

MIDSPAN and AUTO inputs. Changes to those inputs

during normal operation are ignored.

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